digital adder

基本解释

Addend and the summand input, and digital and carry the output device is a half adder.
加法器是産生數的和的裝置。加數和被加數爲輸入，和數與進位爲輸出的裝置爲半加器。
A digital adder needs more circuitry, and thus more power, to operate, but it does not require such high accuracy.
數字加法器需要更多的電路、因而需要更大的功率才能工作，但它不需要這麽高的準確性。
We take the Full Adder as an example to introduce the use of VHDL in the design of digital system, the experiment of digital circuit and the teaching.
本文以全加器爲例介紹其在數字系統設計和數字電路實騐及教學中的應用。