CPPLL
基本解释
- 電荷泵鎖相環
英汉例句
- And finally, a clock generator based on the 3rd order CPPLL is fully designed with UMC 0.25 CMOS process.
最後,採用UMC 0.;25 CMOS工藝技術設計了一個用作時鍾産生的三堦電荷泵鎖相環。 - The application of my CPPLL is deserializer in video system, sampling high frequency data by low frequency clock to generate parallel low frequency data output.
通過對時鍾的頻率和相位的同步,多相位輸出,來對高速串行數據進行解串,輸出低速竝行信號。 - 4th order CPPLL
4堦電荷泵鎖相環